FPGA IMPLEMENTATION OF MULTIBIT FLIP-FLOP USING MESOCHRNOUS TECHNIQUE

Abstract

To make the system more modular and to make timing closure simpler, mesochronous clocking replaces strict synchronisation with more flexible clocking mechanisms. The clock signals that arrive at the two ends of the mesokronous interface have the same frequency, but there may be an unknown phase connection between the arrival clock signals on the margins. Sending data between modules requires clock synchronisation. First, in this brief, we offer a unique mesochron FIFO that can handle clock synchronisation and temporary data storage, synchronising data implicitly via explicit flow control synchronisation. The recommended method can work even if the transmitter and receiver are separated by a long link, such that the delay does not fit within the specified operating frequency. Multi-cycle connections may be accommodated using the recommended mesochronous FIFO, which is easily modifiable without affecting the basic concept. An implementation of the new design is proven to have a much lower cost compared to previous state of the art mesochronous FIFO architectures.